1. Technical Field
Various exemplary aspects of the present invention relate to semiconductor apparatuses and related methods. In particular, certain exemplary aspects relate to a three-dimensional semiconductor apparatus.
2. Related Art
In order to increase the degree of integration of a semiconductor apparatus, a 3D (three-dimensional) semiconductor apparatus has been developed. The 3D semiconductor apparatus includes a package of a plurality of stacked chips. The 3D semiconductor apparatus may achieve a maximum degree of integration in the same space by vertically stacking two or more chips.
The 3D semiconductor apparatus may be realized in a variety of ways. For example, a plurality of chips having the same structure may be stacked and connected together by wires such as metal wires, and are able to operate as a single semiconductor apparatus.
Recently, a TSV (through-silicon via) type semiconductor apparatus has been proposed. In a TSV type semiconductor apparatus, silicon vias are formed to pass through a plurality of stacked chips so that all the chips are electrically connected together. Since the through-silicon vias vertically pass through the respective chips in the TSV type semiconductor apparatus, the size of a package may be efficiently decreased compared to the semiconductor apparatus in which respective chips are connected through the wires.
The typical TSV type semiconductor apparatus is composed of a master chip and a plurality of slave chips which are electrically connected with the master chip through TSVs. For example, the master chip in a memory apparatus includes all logic circuits which are provided for the operation of the memory apparatus in a peripheral circuit region, and each of the slave chips includes its own memory core for data storage and circuits for the operation of the memory cores, so as to operate as a single semiconductor apparatus.
Since the plurality of chips stacked in a 3D semiconductor apparatus operate as a single semiconductor apparatus, they share data input and output. In the wired semiconductor apparatus, the data outputted from respective stacked chips may be transmitted to a controller through input/output lines. The data stored in the slave chips in a TSV semiconductor apparatus may be transmitted to the master chip and thereafter outputted externally through pads disposed on the master chip. In order to improve the operating speed of the semiconductor apparatus, it may be necessary to make the output timing of the data transmitted from the stacked chips coincide.
However, because the stacked chips have different characteristics due to variations in PVT (process, voltage and temperature), it may be difficult to manufacture them with a similar performance. More specifically, different PVT properties of the stacked chips create skews between the respective chips. Thus, a skew in data output timing may result between a chip having a high operating speed and a chip having a low operating speed. In order to secure a data valid window in the existence of the skew, the operating speed of the semiconductor apparatus should be lowered, which may not be desirable.
FIG. 1 is a diagram schematically illustrating the configuration of a conventional semiconductor apparatus. In FIG. 1, a semiconductor apparatus may be composed of first to third chips c1-c3. The first chip c1 operates as a master chip, and the second and third chips c2 and c3 operate as slave chips. The master chip c1 includes a command buffer 11, a data input buffer 13, a data alignment unit 15, a pipe latch unit 14, and a data output buffer 16. The slave chips c2 and c3 respectively include core units 21 and 31, write drivers 22 and 32, read drivers 23 and 33, and delay units 24 and 34.
The read and write operations of the semiconductor apparatus will be described below. In the read operation, a read command RD is externally applied to the command buffer 11, generating an internal read command RD_int from the read command RD. The internal read command RD_int is transmitted to the second and third chips c2 and c3 through first TSVs TSV1. The second and third chips c2 and c3 generate column control signals iostb and yi from the internal read command RD_int through the first and second delay units 24 and 34. In response to the column control signals iostb and yi, the data stored in the core units 21 and 31 are outputted to the read drivers 23 and 33. The read drivers 23 and 33 amplify the data and output the amplified data to data input/output lines GIO_c2 and GIO_c3. The data input/output lines GIO_c2 and GIO_c3 of the second and third chips c2 and c3 are connected with each other through second TSVs TSV2, and the data outputted from the second and third chips c2 and c3 are inputted to the pipe latch unit 14 of the first chip c1. The pipe latch unit 14 aligns the data transmitted through the second TSVs TSV2, and the data output buffer 16 buffers the aligned data and outputs the buffered data to a pad 17.
In the write operation, as a write command WT is applied to the command buffer 11, generating an internal write command WT_int. The internal write command WT_int may then be transmitted to the second and third chips c2 and c3 through the first TSVs TSV1. The data applied from the pad 17 may be transmitted to the second TSVs TSV2 through the data input buffer 13 and the data alignment unit 15. Accordingly, the write drivers 22 and 32 of the second and third chips c2 and c3 buffer the data applied through the second TSVs TSV2 and the data input/output lines GIO_c2 and GIO_c3 in response to column control signals wtstb and yi which are generated from the internal write command WT_int by the delay units 24 and 34. The buffered data are stored in the core units 21 and 31.
As illustrated above, the plurality of chips constituting the single semiconductor apparatus share the data input/output lines. Therefore, the timing when the data are outputted from the respective chips or the the data are stored in the respective chips should coincide with each other so as to secure a data valid window. However, because the characteristics of the respective chips are different due to variations in PVT, it is difficult to make the input and output timing of the data coincide with each other.